1. FIELD OF THE INVENTION
This invention relates to a drive circuit for an inductive load and, more specifically, to a negative voltage clamp circuit for controlling currents in inductive loads, particularly solenoids.
2. BRIEF DESCRIPTION OF THE PRIOR ART
Solenoids are useful in many areas, such as, for example, in conjunction with automobile transmissions and the like. It is desirable to provide a solenoid, preferably but not solely for use in such transmissions, which are capable of rapid operation. In this regard, it is necessary to provide a drive circuit for the solenoid which initially furnishes high drive current for fast solenoid pull-in or turn on and then furnishes lower drive current for hold-in of the solenoid for continuous solenoid operation thereafter. The lower hold-in current is desirable because the high current required for fast pull-in is no longer necessary and results in a decrease of power dissipation. Also, when operating at the lower current, and for example, changing to a different solenoid drive in the transmission, the solenoid can be completely disabled or drop out more rapidly as compared with operation at the higher pull-in current due to the storage of less energy in the coil of the solenoid. Accordingly, it is desirable that the solenoid have fast pull-in lower current and hold-in and fast drop out.
It is also desirable that the circuit include diagnostics and fail-safe types of information and control either during or prior to commencement of solenoid drive circuit operation to avoid operation which could damage the solenoid and/or associated circuitry.
Applicants herein are unaware of any prior art that performs the above desired functions or of any prior art that permits the control of relatively large recirculating current (about 6 amperes) below a junction isolated substrate potential (p-type substrate) with negative voltages in excess of -2 volts. Applicants are aware of high-side drivers which can provide large negative going transients (below substrate voltage) for the fast collapse of inductive loads. However, a higher on-chip power dissipation occurs when using that approach.